A Study on Hardware Design for High Performance Artificial Neural Network by using FPGA and NoC

Artificial neural networks (ANNs) are widely used in various applications such as recognition, security, computer learning and so on. To meet requirements of higher performance, hardware implementations have been widely researched and developed. The popular implementation methods are FPGA, analog, digital and hybrid methods. The FPGA method is widely used due to the low cost and short design time, but at the same time it is limited by the performance compared with other hardware implementation methods. The digital method is also widely used due to high precision, good expansibility and a good design support by EDA tools, but at the same time it is limited by the higher design cost, heavy communication load and less reconfigurability. In this thesis, we formulate and address problems in these two key hardware implementation methods, namely, FPGA ANN and digital ANN. The first problem is the performance problem limiting the development of FPGA ANN. We presented a novel architecture for the FPGA ANN, which integrates both the layer-multiplexing and pipeline architecture. This proposed architecture could achieve high performance by enhancing the efficiency of resource usage of the same FPGA board. Our proposed architecture presents an advantage in two basic respects over the traditional implementations. The first one is the hybrid of layer multiplexing and pipeline, which can optimize both the resource requirement and speed. The layer multiplexing guarantees the resource required by neural network under the constraint of an adopted FPGA chip, and the pipelining between the layers can improve the speed. The second point is the algorithm to determine the optimal hardware architecture according to the neural network parameters such as the topology, data structure and so on. Furthermore, our method just meets the resource limitation of a given FPGA, so that the FPGA board does not need to be changed for another application. The second is a problem in digital ANN which is limited by the higher design cost, heavy communication load and less reconfigurability. Recently, Network on Chip (NoC) has attracted much attention. The packet-based network with high level parallelism architecture of NoC was used to solve complex on-chip interconnection problems for large system-on-chip (SoC). We presented a digital ANN with NoC architecture to solve the existing problems of digital ANN, such as heavy communication load and less reconfigurable. This digital ANN with NoC architecture is reconfigurable, because the weight values and activation functions can be changed as desired. We can also change the topology and routing algorithms of the NoC by sending new data to meet different kinds of ANN, so this system is easily extended. We can design this system in the style of cell-by-cell and i